Customer Success: Integrating VTOS with Boundary Scan
Recently we worked with a customer who needed additional circuit board test and fault coverage. They were gearing up for the production of a new medical device and needed critical test coverage for a few keys aspects of their design. Kozio delivered an embedded test solution in three days that integrated beautifully with their boundary scan solution; delivering the requested fault coverage and more.
How It All Started
We first engaged with this customer based on a request for a solution providing USB validation. The customer had a Boundary Scan solution in place and was happy with the tools and process; but needed test coverage for additional aspects of the design not covered by 1149.1 boundary scan testing. The customer looked at other options first, which required months developing new software for USB testing, but were not able to get the resources they needed in the time frame they needed.
Kozio’s proposal was to deliver a proven, documented solution in three (3) days. A solution named VTOS that provided coverage above and beyond USB. Other critical benefits that the Kozio team brought to the table were: domain experience, decades of firmware development on multiple processor architectures and hundreds of PCB designs, and industry contacts with all the major silicon providers.
Boundary Scan (JTAG) Integration
Besides test coverage, the other request was to have the embedded test solution integrate nicely with the existing Boundary Scan tools being used by the customer. What Kozio delivered was a binary executable that runs from Flash memory, runs all user-defined test cases, and then stores test results to a separate Flash memory location.
The slick part of the solution was the flexibility along with the very simple integration, a solution that can apply to other PCB designs. The user defines which tests they want to run in a script file. For development, they use Integration Workbench™, Kozio’s interactive GUI, to verify that the script performs all the desired test cases. Kozio provided a draft script file along with documentation on how to alter or amend the test capabilities. That script file is programmed into Flash memory by the JTAG tools, along with VTOS. The JTAG tool resets the unit under test, VTOS runs, loads the script file, executes all test cases, and programs test results back into Flash. The final step is for the JTAG tool to read the test results from Flash and present them to the test operator.
The total execution time for VTOS to boot, run all tests in the production test script, and store results was 15 seconds. The customer can use the above process to optimize test execution and reduce the test time further, without sacrificing test coverage.
In order to coordinate timing with the JTAG tools, VTOS was scripted to drive multiple GPIO signals. VTOS would drive one GPIO signal to indicate a successful boot, then drive another GPIO signal to indicate successful test starting, and a third GPIO signal to indicate that the production test script completed and results were stored. The JTAG tool monitored those signals in order to provide status to the operator and to know when to read the test results. From the operator’s perspective, the entire test flow from boundary can testing to embedded testing, was seamless.
Test Coverage Information
Here is a quick overview of the tests provided with the delivery:
- USB: disable/enable test, enumeration test, device discovery test, and speed detection test
- DDR SDRAM: verify data bus lines, verify address lines, stress the data bus, verify the SDRAM device, verify data caching and bursting, and verify all memory cells
- NOR Flash: program test, buffer program test, erase test, lock test, and memory data pattern test
- ECC: single bit error read/write test, walking single bit error read/write test, multiple bit error read/write test
- UART: data path walking 0/1 test, interrupt test, external loopback test
- RTC: The standard VTOS tests were extended to cover testing a Real Time Clock (RTC) accessed through a CPLD register interface
- FPGA: The VTOS memory test algorithms were reused to test a scratch register in the FPGA, validating at full speed the interface
- CPLD: The VTOS memory test algorithms were reused to test a scratch register in the CPLD, validating at full speed the interface
- Ethernet: enable/disable interface test, selftest, PHY scanning test, 10/100/1G PHY loopback with packet data verification, 10/100/1G MAC loopback with packet data verification, and 10/100/1G external (off board) loopback with packet data verification
All in all, this was a fun customer delivery with great results. The customer was very pleased with the results and increased test coverage, and the solution integrated nicely with the Boundary Scan tool chain.
This customer success story illustrates how effectively VTOS can be configured and extended to integrate with third-party tools such as Boundary Scan tools, providing great test coverage quickly. Please feel free to comment or contact us to discuss how it may help with your production test needs.