Standard, high-coverage, high-integrity tests run on your custom circuit board

Commands are provided to:

Test suites are provided to calculate performance (caching and non-caching), and execute extensive tests (address, burst, byte, walking 0’s, walking 1’s, word, and data line tests). Both quick and full versions of SDRAM test are provided. Both read and write operations are performed on byte, word, short, and long aligned accesses. In addition, these operations are performed on both cached memory and non-cached memory locations.

Individual test cases include:

Serial Presence Detect comprises a tiny serial EEPROM mounted on the memory module, containing the characteristics, features, and attributes of the memory module being used. The memory manufacturer programs the SPD during the manufacturing process. kDiagnostics automatically reads the memory’s SPD data and adjusts its own diagnostics settings to match. All SDRAM tests can then be used to validate the entire memory region. This feature allows the customer to quickly test any hardware-appropriate memory module (SIMM, DIMM, SODIMM, or SIMM).

These kDiagnostics commands verify the functionality of EEPROM components connected via an I2C interface. Two types of EEPROM devices are supported – general purpose EEPROMs and SDRAM EEPROMs. Users may program the EEPROM with data from any other memory location, either interactively, or via an automatically executed script.

These commands operate on flash parts that conform to the Common Flash Interface (CFI) specification. The CFI parameters are used to determine which family of programming algorithms is used. The CFI information also specifies the specific flash implementation operating parameters: flash part size, data bus width, and erase block size. Numerous flash test routines are provided to:

These commands provide a configurable and extensible set for testing various memory types. Each memory test is configured with a starting memory location and a data-bus width. The memory address bus and memory cell tests are also configured with an ending memory location. In general, one should execute memory tests in the following sequence: data-bus tests, address-bus tests, and memory cell tests. In addition, kDiagnostics also provides memory read performance tests and a memory write performance test. Methods are provided for reuse such as a memory validation routine, a memory dump routine, a memory fill routine, a memory verify routine, and a number of memory dump commands (general, ASCII, byte, short, word). Also provided are commands to read and write memory (long, word, byte, and short).

kDiagnostics standalone (self-booting) code can automatically perform SDRAM scrubbing for platforms that implement ECC. kDiagnostics validates single bit error detection/correction as well as multiple bit error detection during both normal read access and read-modify-write access.

Automatically determines DDR SDRAM controller timing window values and qualifies memory operations using those timing values.

Commands can exercise several components in concert, including the source and destination devices, CPU, DMA controller, memory controllers, and busses. The source address, destination address, data patterns, initialization modes and length are configurable. Several DMA transfers can be chained together in a single DMA operation or performed concurrently on separate DMA channels. DMA performance can be measured over any bus between any two memory regions. All tests verify that DMA transfers complete successfully without data corruption.

Commands verify general operation of the PCI bus supports conventional PCI, PCI-X, and PCI-Express. The underlying PCI driver is capable of performing discovery on the PCI bus/link and can also automatically configure the memory and I/O areas for each device found. These commands support multiple PCI busses/links attached directly to the processor (multiple primary busses) as well as multiple PCI busses/links connected through PCI bridges.

Both Parallel RapidIO and Serial RapidIO connection topologies are supported by kDiagnostics. Low-level commands provide support for initializing RapidIO hosts, performing device discovery/enumeration, as well as automatic configuration of recognized RapidIO device types. For implementations with a fixed topology, device enumeration can optionally be skipped by manually configuring RapidIO device identifiers. Low-level commands are available for initiating maintenance reads and writes, providing access to the RapidIO capability registers (CARs) and command and status registers (CSRs). Finally, the low-level interface provides a mechanism for configuring the outbound RapidIO transaction type and size for each discovered RapidIO device.

Diagnostics testing includes verification of maintenance read/write transactions to all discovered devices. If specific RapidIO devices in the switch fabric provide general purpose memory, the memory test methods can be used to verify other RapidIO transaction types such as NREAD and NWRITE.

Tests and commands are provided to perform:

These tests require that an external USB host be connected to the USB device when prompted. If the test passes, the device has successfully received and sent packets on the control endpoint.

Commands and test suites are provided to scan for I²C attached devices, initializing access to a device, reading a block, reading a byte from a device, writing a byte to a device, and dumping I²C information. Executing I²C test suites verifies that communication is working with all known I²C devices. Support is included for devices such as EEPROMs, Real Time Clocks (RTC), temperature sensor, and others. Other test suites use the I²C interface to perform their testing, providing further validation of that particular I²C interface. Using the I2C commands provided by Kozio, the user can communicate and test any I²C connected device by creating a new test script and executing it in real-time.

The tests of this section are used to verify packet transmission and reception through a 10/100/1000 MAC, MII, PHY, loopback plug, or onto a local area network (LAN). For chips that offer additional functionality, suites are provided for self-testing and display of internal chip-based statistics. Test suites are provided for all discovered or known interfaces. Discovered interfaces can be Network Interface Cards (NICs) that are bus-based and supported. In addition, support is provided to test through a switch device that is included as part of the board design.

Commands are provided to:

Using the GPIO commands provided by Kozio, the user can communicate and test any GPIO-connected device by creating a new test script and executing it in real-time.

These commands verify operation of internal and external timers against the internal clock of the CPU. This test records a timestamp using the specified timer to mark the test start time. Next, the test records 5 additional timestamps. In between each timestamp, the test delays 1 second using a tight calculated loop. At the completion, the time difference between timestamps is measured and calculated. The test passes if the average difference between timestamps is within 1 millisecond of a 1 second difference.

These commands verify the data path to and from UART (Universal Asynchronous Receiver-Transmitter) devices and also verify the interrupt connection back to the core processor. The data path is verified by running walking zeroes and walking ones tests against the UART scratch register.

Pre-configured tests and test methods are provided to test generic modem and similar RS-232 functionality. Low-level commands are provided to support creating custom modem tests and a terminal emulator for direct interaction with the modem.

FPGA image loading is provided for numerous FPGA components, such as Xilinx and Altera, as well as register access to the FPGA or ASIC. Custom test suites can be developed by Kozio, based on a specification of logic and a separate NRE fee or by customers using kDiagnostics Design Suite Pro.

Commands verify the operation of audio devices, including I2S and PCM-based audio codecs. Standard tests are provided to play fixed tones to various audio outputs, record audio from various audio inputs, and play back recorded audio. Commands are provided to configure various audio test parameters, including sample rate, bit depth, and input and output gain.

These commands verify the higher level functionality of voice channels utilizing SLIC (Subscriber Line Interface Circuit) components. Tests in this category validate data transfer to and from SLICs using the high-speed serial interface. Tests include voice recording and playback from a connected telephone and DTMF (Dual Tone Multiple Frequency) tone generation and detection (also known as touch tone dialing). Low level commands are available for generating dial tones, busy signals and can also be used to generate a perfect 1 kHz test tone. In general, a voice channel must first be enabled before using any of the commands in this category.

Commands verify the operation of display devices, including VGA, WVGA, HDMI, and TV (S-video) display devices. Standard tests for each display type are provided, as well as methods for drawing various test patterns to the displays.

Commands verify the operation of a SATA controller using IDE mode commands to read and write to a connected device. Also provided is random access to the connected device.

Additional optional tests verify I/O and measure performance to one or more block-based storage devices. Commands and tests are provided to verify interrupts associated with a channel, to perform a write, read, and verify test to a discovered target device, and to verify sequential write operations, as well as random write operations. Data verification tests can be performed in polled mode as well as interrupt-driven mode. Various configuration methods are provided for such features as ramp-up time. Additional methods include the ability to discover target devices, add workers for I/O streams, display discovered target devices, execute a polled read command, and a polled write command. I/O worker threads are created to perform random reads, sequential reads, random writes, and sequential writes. If target devices are not connected to the target platform, pseudo-target objects can be enabled and used for I/O performance characterization.

Commands verify I/O to one or more block-based storage devices. Commands and tests are provided to verify interrupts associated with a channel, to perform a write, read, and verify test to a discovered target device, and to verify sequential write operations, as well as random write operations. Data verification tests can be performed in polled mode as well as interrupt-driven mode.